Atmel ATA6837
High Temperature Hex Half-bridge Driver with Serial Input
Control
DATASHEET
Features
● Six half-bridge outputs formed by six high-side and six low-side drivers
● Capable of switching all kinds of loads (such as DC motors, bulbs, resistors,
capacitors and inductors)
● RDSon typically 1.0Ω at 25°C, maximum 2.2Ω at 200°C
● Up to 650-mA output current
● Very low quiescent current IS < 20µA in Standby Mode
● Outputs short-circuit protected
● Overtemperature prewarning and protection
● Undervoltage protection
● Various diagnosis functions such as shorted output, open load, overtemperature
and power supply fail
● Serial data interface
● Operation voltage up to 40V
● Daisy chaining possible
● Serial interface 5V compatible, up to 2MHz clock frequency
● QFN24 package
4953H–AUTO–03/12
1.
Description
The Atmel® ATA6837 is designed for high-temperature applications. In mechatronic solutions, for example, turbo charger or
exhaust gas recirculation systems, many flaps have to be controlled by DC motor driver ICs which are located very close to the
hot engine or actuator and where ambient temperatures up to 150°C are usual. Due to the advantages of SOI technology,
junction temperatures up to 200°C are allowed. This enables new cost-effective board design possibilities to achieve complex
mechatronic solutions.
The Atmel ATA6837 is a fully protected hex half-bridge driver, used to control up to 6 different loads by a microcontroller in
automotive and industrial applications.
Each of the six high-side and six low-side drivers is capable of driving currents up to 650mA. The drivers are internally
connected to form 6 half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of
loads, such as bulbs, resistors, capacitors and inductors, can be combined. The IC especially supports the application of Hbridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions
and a very low quiescent current in standby mode make a wide range of applications possible.
Automotive qualification referring to conducted interferences, EMC protection and ESD protection gives added value and
enhanced quality for the exacting requirements of automotive applications.
Figure 1-1. Block Diagram QFN24
S
I
S
C
T
O
L
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
3, 4
VS
Input register
Ouput register
DI
19
P
S
F
I
N
H
S
C
D
H
S
6
Serial interface
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
Charge
pump
L
S
1
T
P
CLK
18
CS
17
INH
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
UV
protection
Fault
Detect
14
12
Control
logic
DO
13
VCC
Power on
reset
24
GND
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
16
Fault
Detect
GND
Thermal
protection
15
GND
7
11
OUT1
8
5
2
OUT2
OUT3
OUT4
23
OUT5
GND
20
OUT6
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
2
Pin Configuration
NC
OUT5
OUT5 SENSE
OUT6 SENSE
OUT6
DI
Figure 2-1. Pinning QFN 24, 5 × 5, 0.65mm Pitch
OUT4 SENSE
OUT4
VS
VS
OUT3
OUT3 SENSE
1
2
3
4
5
6
24 23 22 21 20 19
18
17
16
15
14
13
7 8 9 10 11 12
CLK
CS
GND SENSE
NC
VCC
DO
NC
OUT2
OUT2 SENSE
OUT1 SENSE
OUT1
INH
2.
Note:
YWW
ATAxyz
ZZZZZ
AL
Table 2-1.
Pin Description QFN24
Pin
1
Symbol
Date code (Y = Year above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Function
OUT4 SENSE Only for testability in final test
Half-bridge output 4; formed by internally connected power MOS high-side switch 4 and low-side
switch 4 with internal reverse diodes; short circuit protection; overtemperature protection;
diagnosis for short and open load
2
OUT4
3
VS
Power supply output stages HS4, HS5 and HS6
4
VS
Power supply output stages HS1, HS2 and HS3
5
6
OUT3
Output 3; see pin 1
OUT3 SENSE Only for testability in final test
7
NC
8
OUT2
Internal bond to GND
Output 2; see pin 1
9
OUT2 SENSE Only for testability in final test
10
OUT1 SENSE Only for testability in final test
11
OUT1
12
INH
Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation
13
DO
Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends
16-bit status information to the microcontroller (LSB is transferred first). Output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate on one data
output line only
14
VCC
15
NC
16
Output 1; see pin 1
Logic supply voltage (5V)
Internal bond to GND
GND SENSE Ground; reference potential; internal connection to the lead frame; cooling tab
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
3
Table 2-1.
Pin Description QFN24 (Continued)
Pin
Symbol
Function
17
CS
Chip select input; 5V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
18
CLK
Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2MHz)
19
DI
20
OUT6
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the
control device; DI expects a 16-bit control word with LSB being transferred first
Output 6; see pin 1
21
OUT6 SENSE Only for testability in final test
22
OUT5 SENSE Only for testability in final test
23
OUT5
24
NC
Output 5; see pin 1
Internal bond to GND
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
4
3.
Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the
falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of CS.
Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB
(bit 0, TP) is transferred first.
Figure 3-1. Data Transfer Input Data Protocol
CS
DI
SRR
0
LS1
HS1
LS2
1
2
3
SLS1
SHS1
SLS2
HS2
LS3
HS3
LS4
4
5
6
7
8
9
10
SHS2
SLS3
SHS3
SLS4
SHS4
SLS5
SHS5
HS4
LS5
HS5
LS6
11
HS6
12
OLD
13
SCT
14
SI
15
CLK
DO
Table 3-1.
TP
SLS6
SHS6
SCD
INH
PSF
Input Data Protocol
Bit
Input Register
Function
0
SRR
Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown
in the output data register are set to low)
1
LS1
Controls output LS1 (high = switch output LS1 on)
2
HS1
Controls output HS1 (high = switch output HS1 on)
3
LS2
See LS1
4
HS2
See HS1
5
LS3
See LS1
6
HS3
See HS1
7
LS4
See LS1
8
HS4
See HS1
9
LS5
See LS1
10
HS5
See HS1
11
LS6
See LS1
12
HS6
See HS1
13
OLD
Open load detection (low = on)
14
SCT
Programmable time delay for short circuit
(shutdown delay high/low = 12ms/1.5ms)
15
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is still
powered)
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
5
Table 3-2.
Bit
Output Data Protocol
Output (Status) Register Function
TP
1
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
3
Status LS2
Description see LS1
4
Status HS2
Description see HS1
5
Status LS3
Description see LS1
6
Status HS3
Description see HS1
7
Status LS4
Description see LS1
8
Status HS4
Description see HS1
9
Status LS5
Description see LS1
10
Status HS5
Description see HS1
11
Status LS6
Description see LS1
12
Status HS6
Description see HS1
13
SCD
Short circuit detected: set high, when at least one output is switched off by a short
circuit condition
14
INH
Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit
(pin INH). High = standby, low = normal operation
15
Note:
Table 3-3.
PSF
Power supply fail: undervoltage at pin VS detected
Bit 0 to 15 = high: overtemperature shutdown
Status of the Input Register After Power on Reset
Bit 15 Bit 14
(SI)
(SCT)
H
Temperature prewarning: high = warning
(overtemperature shutdown see remark below)
0
H
Bit 13
(OLD)
Bit 12
(HS6)
Bit 11
(LS6)
Bit 10
(HS5)
Bit 9
(LS5)
Bit 8
(HS4)
Bit 7
(LS4)
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
H
L
L
L
L
L
L
L
L
L
L
Bit 2 Bit 1
(HS1) (LS1)
L
L
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
Bit 0
(SRR)
L
6
3.2
Power-supply Fail
In case of undervoltage at pin VS, an internal timer is started. When during a permanent undervoltage the delay time (tdUV) is
reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present
again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register.
3.3
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each
low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load
detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on
an output stage with OLD bit set to low disables the open load function for this output.
3.4
Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the
output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP
bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After
the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the
input and output registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output
register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold,
Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold
have hysteresis.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and
shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when
during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the
short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the
shorted output is disabled after tdSd and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset
and the disabled outputs are enabled.
3.6
Inhibit
There are two ways to inhibit the Atmel® ATA6837:
● Set bit SI in the input register to 0
●
Switch pin INH to 0V
In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by
bit SI = 1 (when INH = VCC) or by pin INH switched back to VCC (when SI = 1).
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
7
4.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters
Pin
Symbol
Value
Unit
Supply voltage
3, 4
VVS
–0.3 to +40
V
Supply voltage t < 0.5s; IS > –2A
3, 4
VVS
–1
V
Supply voltage difference
⏐ VS_pin3 – VS_pin4⏐
3, 4
ΔVVS
150
mV
Logic supply voltage
14
VVCC
–0.3 to +7
V
17 - 19
VDI, VCLK, VCS
–0.3 to VVCC +0.3
V
13
VDO
–0.3 to VVCC +0.3
V
12, 17 - 19
IINH, IDI, ICLK, ICS
–10 to +10
mA
Output current
13
IDO
–10 to +10
mA
Output current
2, 5, 8, 11, 20, 23
IOUT1 to IOUT6
Internally limited, see
“Output Specification” in
Section 7. on page 9
Junction temperature range
Tj
–40 to +200
°C
Storage temperature range
TSTG
–55 to +200
°C
Ambient temperature range
Ta
–40 to +150
°C
Logic input voltage
Logic output voltage
Input current
5.
Thermal Resistance
Table 5-1.
QFN24: Depends on the PCB-board
Parameter
Test Conditions
Junction pin
Pin
Symbol
16
Junction ambient
6.
Min.
Typ.
Max.
Unit
RthJP
1ms.
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
9
7.
Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 200°C, Ta ≤ 150°C; unless otherwise specified, all values refer to GND
pins.
No.
Parameters
4.6
Thermal shutdown
hysteresis
4.7
Ratio thermal
shutdown/thermal
prewarning
4.8
5
Test Conditions
Pin
Symbol
Min.
Typ.
Tj switch off
Tj switch off/
Max.
15
Unit
Type*
K
C
1.05
1.2
C
1.05
1.2
C
TjPW set
Ratio thermal
shutdown/thermal
prewarning
Tj switch on/
TjPW reset
Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < 40V
5.1
On resistance
IOut = 600mA
2, 5, 8,
11, 20,
23
RDS OnL
2.2
Ω
A
5.2
On resistance
IOut = –600mA
2, 5, 8,
11, 20,
23
RDS OnH
2.2
Ω
A
5.3
High-side output leakage
VOut1-6 = 0V
current (total quiescent
all output stages off
current see 1.1)
2, 5, 8,
11, 20,
23
IOut1-6
µA
A
5.4
Low-side output leakage
VOut1-6 = VS
current (total quiescent
all output stages off
current see 1.1)
2, 5, 8,
11, 20,
23
IOut1-6
250
µA
A
5.5
Inductive shutdown
energy
2, 5, 8,
11, 20,
23
Woutx
15
mJ
D
5.6
Overcurrent limitation
VVS ≤ 13V
and shutdown threshold
2, 5, 8,
11, 20,
23
ILS1-6
650
950
1400
mA
A
5.7
Overcurrent limitation
VVS ≤ 13V
and shutdown threshold
2, 5, 8,
11, 20,
23
IHS1-6
–1400
–950
–650
mA
A
5.8
Overcurrent limitation
20V < VVS < 40V
and shutdown threshold
2, 5, 8,
11, 20,
23
ILS1-6
650
950
1600
mA
C
5.9
Overcurrent limitation
20V < VVS < 40V
and shutdown threshold
2, 5, 8,
11, 20,
23
IHS1-6
–1600
–950
–650
mA
C
5.10
Overcurrent shutdown
delay time
Input register
bit 14 (SCT) = low
VVS = 13V
tdSd
0.9
1.5
2.1
ms
A
5.11
Overcurrent shutdown
delay time
Input register
bit 14 (SCT) = High
VVS = 13V
tdSd
7
12
17
ms
A
5.12
High-side open load
detection current
Input register bit 13
(OLD) = low, output off
IOut1-3H
–1.6
–0.3
mA
A
2, 5, 8,
11, 20,
23
–60
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1ms.
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
10
7.
Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 200°C, Ta ≤ 150°C; unless otherwise specified, all values refer to GND
pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
5.13
Low-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 5, 8,
11, 20,
23
IOut1-3L
0.3
5.14
Open load detection
current ratio
2, 5, 8,
11, 20,
23
IOLoutLX/
IOLoutHX
1.05
5.15
High-side open load
detection voltage
Input register bit 13
(OLD) = low, output off
2, 5, 8,
11, 20,
23
VOut1-6H
0.5
5.16
Low-side open load
detection voltage
Input register bit 13
(OLD) = low, output off
2, 5, 8,
11, 20,
23
VOut1-6L
0.5
5.17
High-side output switch
on delay(1)
VVS = 13V
RLoad = 30Ω
5.18
Low-side output switch
on delay(1)
5.19
Max.
Unit
Type*
1.6
mA
A
2.5
V
A
2.2
V
A
tdon
20
µs
A
VVS = 13V
RLoad = 30Ω
tdon
20
µs
A
High-side output switch
off delay(1)
VVS =13V
RLoad = 30Ω
tdoff
20
µs
A
5.20
Low-side output switch
off delay(1)
VVS =13V
RLoad = 30Ω
tdoff
3
µs
A
5.21
Dead time between
V =13V
corresponding high- and VS
RLoad = 30Ω
low-side switches
6
Typ.
1.2
2
tdon – tdoff
1
µs
A
0.3 ×
VVCC
V
A
0.7 ×
VVCC
V
A
Inhibit Input
6.1
Input voltage low-level
threshold
12
VIL
6.2
Input voltage high-level
threshold
12
VIH
6.3
Hysteresis of input
voltage
12
ΔVI
100
700
mV
A
6.4
Pull-down current
IPD
10
80
µA
A
0.3 ×
VVCC
V
A
0.7 ×
VVCC
V
A
7
VINH = VVCC
Serial Interface: Logic Inputs DI, CLK, CS
7.1
Input voltage low-level
threshold
17 - 19
VIL
7.2
Input voltage high-level
threshold
17 - 19
VIH
7.3
Hysteresis of input
voltage
17 - 19
ΔVI
50
500
mV
A
7.4
Pull-down current pin DI,
VDI, VCLK = VVCC
CLK
18 - 19
IPDSI
2
50
µA
A
7.5
Pull-up current pin CS
17
IPUSI
–50
–2
µA
A
VCS= 0V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1ms.
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
11
7.
Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 200°C, Ta ≤ 150°C; unless otherwise specified, all values refer to GND
pins.
No.
8
8.1
Parameters
Test Conditions
Pin
Symbol
13
VDOL
Min.
Typ.
Max.
Unit
Type*
0.5
V
A
V
A
µA
A
Serial Interface: Logic Output DO
Output voltage low level IOL = 3mA
8.2
Output voltage high level IOL = –1mA
13
VDOH
VVCC –
0.7V
8.3
Leakage current
(tri-state)
13
IDO
–10
VCS = VVCC,
0V < VDO < VVCC
10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1ms.
8.
Serial Interface: Timing
Parameters
Test Conditions
Pin
Timing Chart No.
Symbol
Min. Typ. Max. Unit
DO enable after CS falling edge CDO = 100pF
13
1
tENDO
200
ns
DO disable after CS rising edge CDO = 100pF
13
2
tDISDO
200
ns
DO fall time
CDO = 100pF
13
-
tDOf
100
ns
DO rise time
CDO = 100pF
13
-
tDOr
100
ns
DO valid time
CDO = 100pF
13
10
tDOVal
200
ns
CS setup time
17
4
tCSSethl
225
ns
CS setup time
17
8
tCSSetlh
225
ns
CS high time
Input register bit 14 (SCT) = high
17
9
tCSh
17
ms
CS high time
Input register bit 14 (SCT) = low
17
9
tCSh
2.1
ms
CLK high time
18
5
tCLKh
225
ns
CLK low time
18
6
tCLKl
225
ns
CLK period time
18
-
tCLKp
500
ns
CLK setup time
18
7
tCLKSethl
225
ns
CLK setup time
18
3
tCLKSetlh
225
ns
DI setup time
19
11
tDIset
40
ns
DI hold time
19
12
tDIHold
40
ns
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
12
Figure 8-1. Serial Interface Timing Diagram with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.2 × VCC
Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
13
9.
Noise and Surge Immunity
Parameters
Test Conditions
Value
Conducted interferences
ISO 7637-1
Level 4(1)
Interference suppression
VDE 0879 Part 2
Level 5
ESD (Human Body Model)
ESD S 5.1
4kV
CDM (Charge Device Model)
ESD STM5.3
500V
MM (Machine Model)
Note:
1. Test pulse 5: Vvbmax = 40V
ESD STM5.2
200V
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
14
10.
Application Circuit
Figure 10-1. Application Circuit
S
I
VCC
O
L
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
VS
S
R
R
BYT41D
VS
Input register
Ouput register
Trigger
Reset
U5021M Enable
Watchdog
S
C
T
Vbatt
24V
+
Serial interface
Charge
pump
GND
DI
P
S
F
I
N
H
S
C
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
GND
GND
CLK
Microcontroller
GND
CS
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
VCC
UV
protection
Fault
Detect
INH
Control
logic
DO
VCC
Power on
reset
VCC
5V
+
GND
VCC
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
GND
Thermal
protection
GND
GND
OUT1
M
10.1
OUT2
M
OUT3
M
OUT4
M
OUT5
OUT6
M
Application Notes
●
●
Connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22µF in parallel with a ceramic capacitor C = 100nF. Value for electrolytic capacitor depends on
external loads, conducted interferences and reverse-conducting current IHSX (see Section 4. “Absolute Maximum
Ratings” on page 8).
●
Recommended value for capacitors at VCC:
Electrolytic capacitor C > 10µF in parallel with a ceramic capacitor C = 100nF.
●
To reduce thermal resistance, place cooling areas on the PCB as close as possible to GND pins and to the die paddle in
QFN24.
●
The sense pins OUTx SENSE can either be left open or can be connected to the adjacent OUTx pin. Never use the
sense pins OUTx SENSE as power outputs.
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
15
Ordering Information
Extended Type Number
Package
ATA6837-PXQW
Remarks
Taped and reeled, Pb-free
Package Information
Package: QFN 24 - 5 x 5
Exposed pad 3.6 x 3.6
(acc. JEDEC OUTLINE No. MO-220)
Dimensions in mm
Not indicated tolerances ±0.05
5
0.9±0.1
+0
3.6
0.05-0.05
24
19
1
24
18
6
0.3
12.
QFN24
0.4
11.
1
technical drawings
according to DIN
specifications
13
6
12
7
0.65 nom.
Drawing-No.: 6.543-5122.01-4
Issue: 1; 15.11.05
3.25
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
16
13.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
4953H-AUTO-03/12
• Section 3.5 “Short-circuit Protection” on page 7 changed
4953G-AUTO-03/11
• Section 10.1 “Application Notes” on page 15 changed
4953F-AUTO-02/10
• Section 7 “Electrical Characteristics” numbers 5.10 and 5.11 on page 10 changed
4953E-AUTO-09/09
• Section 7 “Electrical Characteristics” number 1.7 on page 9 added
• Features on page 1 changed
• Table 2-1 “Pin Description QFN24” on pages 3 to 4 changed
• Section 4 “Abs.Max.Ratings” on page 8 changed
• Section 5 “Thermal Resistance” on page 8 changed
4953D-AUTO-10/08
• Section 6 “Operating Range” on page 8 changed
• Section 7 “Electrical Characteristics” numbers 1.1, 1.2, 1.6, 4.1 to 4.7, 5.3, 5.4 and 5.6 to
5.9 on pages 9 to 10 changed
• Section 8 “Serial Interface: Timing” on page 12 changed
• Section 9 “Noise and Surge Immunity” on page 16 changed
• Section 11 “Ordering Information” on page 14 changed
4953C-AUTO-09/07
• Section 7 “Electrical Characteristics” numbers 5.15 and 5.16 on page 10 changed
• Section 9 “Noise and Surge Immunity” on page 14 changed
• Put datasheet in a new template
4953B-AUTO-07/07
• Section 7 “Electrical Characteristics” numbers 1.5, 3.1, 5.15 and 8.2 on pages 9 to 11
changed
Atmel ATA6837 [DATASHEET]
4953H–AUTO–03/12
17
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